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CVW Architectural Verification

DeprecatedOpenHW Explorer editorial assessment

cvw-arch-verif is the former architectural-verification workspace for CORE-V Wally, containing test plans, covergroups, and directed tests for RVA22S64 and related RV32 extensions. The repository is deprecated and its tests, coverage material, and maintained framework have moved to riscv-arch-test. Use this code only for historical context or migration work; current architecture-testing work should start in the upstream RISC-V repository.

Reviewed profileOfficial sourcesVerified 2026-07-164 sourcesPrimary source
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Category: VerificationStatus: Editorial · DeprecatedBest for: Engineer
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At a glance

  • Status: deprecated repository retained for historical reference
  • Successor: tests, coverage, and the maintained framework moved to riscv-non-isa/riscv-arch-test
  • Original scope: architecture functional verification for CORE-V Wally
  • Contents: test plans, covergroups, and directed tests for RVA22S64 and corresponding RV32 extensions
  • Method boundary: architecture tests and functional coverage, not a formal-verification framework

Further resources

RISC-V architecture testscurrent home for the migrated workCORE-V Wallyprocessor repository targeted by the original verification projectCVW test plancurrent core-level verification planning material
20stars
40forks
SystemVerilogrepository language (GitHub)
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Categories

Verification

Tags

OpenHWRISC-VVerificationArchitecture TestsISA ComplianceArchitectural VerificationSystemVerilogWally

Suitable For

EngineerResearcher

Verification Type

Architecture Tests

Contribution ActivityLow Activity

26

Contributors

9

Open Issues

0

Recent Commits (4 weeks)

1

Open PRs

Data as of Sep 28, 2026

Verified adoption, contributor and lineage records, educational use, presentations, articles, and ecosystem data will be added incrementally from named sources.

Related Projects

CVW (Wally)

CVW, also known as CORE-V Wally, is a configurable five-stage SystemVerilog RISC-V processor that spans minimal RV32E designs through feature-rich RV64GC application processors. It combines a broad extension set with optional caches, branch prediction, virtual memory, and standard platform peripherals, and it can boot Linux on FPGA. Its close connection to the RISC-V System-on-Chip Design textbook, examples, and regression flows makes it especially approachable for students while retaining enough configurability for architecture and SoC research.

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