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CVW, also known as CORE-V Wally, is a configurable five-stage SystemVerilog RISC-V processor that spans minimal RV32E designs through feature-rich RV64GC application processors. It combines a broad extension set with optional caches, branch prediction, virtual memory, and standard platform peripherals, and it can boot Linux on FPGA. Its close connection to the RISC-V System-on-Chip Design textbook, examples, and regression flows makes it especially approachable for students while retaining enough configurability for architecture and SoC research.
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Category: Processor CoresStatus: OpenHW · ActiveBest for: Student
At a glance
- Architecture: five-stage SystemVerilog processor configurable for RV32 or RV64
- Configuration range: minimal RV32E through RV64GC with RVA22S64-profile features
- Optional system features: caches, branch prediction, virtual memory, PMP, CLINT, PLIC, UART, and GPIO
- Demonstrated capability: passes RISC-V architecture tests and boots Linux in simulation and on FPGA
- Readiness and learning context: currently identified as TRL-4 and developed alongside a textbook, setup scripts, examples, tests, and regression flows
Further resources
RISC-V System-on-Chip Design (1st edition, 2026)Morgan Kaufmann textbook, published July 1, 2026; ISBN 978-0-323-99498-9Textbook companion resourcesauthor-maintained lecture slides, labs, sample chapters, exercises, and links to CORE-V WallyTextbook erratacorrections maintained alongside the CVW repositoryCVW test planverification scope and coverage planningCVW Linux guideLinux build and test-vector workflow maintained in the repositoryCORE-V family overviewofficial family positioning for Wally
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SystemVerilogrepository language (GitHub)
Categories
Processor CoresLearning-friendly
Tags
OpenHWRISC-VCoreLearning-friendlyApplication-classEmbedded-classEducationTextbookConfigurableSystemVerilog
Suitable For
StudentResearcherEngineerContributor
Architecture / Focus
Application-classEmbedded-class
Contribution ActivityHighly Active
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Contributors
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Open Issues
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Recent Commits (4 weeks)
26
Open PRs
Data as of Sep 28, 2026
Verified adoption, contributor and lineage records, educational use, presentations, articles, and ecosystem data will be added incrementally from named sources.
Related Projects
CVW Architectural Verification
cvw-arch-verif is the former architectural-verification workspace for CORE-V Wally, containing test plans, covergroups, and directed tests for RVA22S64 and related RV32 extensions. The repository is deprecated and its tests, coverage material, and maintained framework have moved to riscv-arch-test. Use this code only for historical context or migration work; current architecture-testing work should start in the upstream RISC-V repository.
CVA6
CVA6 is a configurable six-stage, in-order CORE-V processor family for 32-bit and 64-bit embedded and application-class systems. Its RTL includes both single-issue configurations, such as CV32A60X, and dual-issue configurations, such as CV32A65X. ISA extensions, privilege modes, and virtual memory depend on the selected configuration: application configurations can run Linux, while the embedded CV32A60X and CV32A65X configurations have no MMU or S/U modes. The repository brings together processor RTL, verification, FPGA integration, and documentation for engineers evaluating a core or exploring custom extensions through CV-X-IF.