Back to ProjectsStart with docsInteractive project guide · DemoCVA6: Capabilities, Systems and Evidence
CVA6 is a configurable six-stage, in-order CORE-V processor family for 32-bit and 64-bit embedded and application-class systems. Its RTL includes both single-issue configurations, such as CV32A60X, and dual-issue configurations, such as CV32A65X. ISA extensions, privilege modes, and virtual memory depend on the selected configuration: application configurations can run Linux, while the embedded CV32A60X and CV32A65X configurations have no MMU or S/U modes. The repository brings together processor RTL, verification, FPGA integration, and documentation for engineers evaluating a core or exploring custom extensions through CV-X-IF.
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Category: Processor CoresStatus: OpenHW · ActiveBest for: Engineer
At a glance
- Architecture: six-stage, in-order family; CV32A60X is single-issue and CV32A65X is dual-issue in the reviewed RTL
- Configuration boundary: ISA extensions, S/U privilege modes, MMU, TLBs, and page-table walking are configuration-dependent, not universal family features
- Embedded examples: CV32A60X and CV32A65X disable the MMU, S/U modes, and A extension; select an appropriate application configuration for Linux
- Readiness: CV32A60X v5.3 has achieved OpenHW TRL-5; readiness must be checked per configuration rather than assumed for the whole family
- Ecosystem: user manual, verification environment, FPGA APU, tutorials, CV-X-IF support, and a performance model for microarchitecture studies
Further resources
CVA6 User Manualofficial documentation on ReadTheDocsCORE-V family roadmap & release tablefamily configurations, TRL status, marchid assignmentsCVA6 ecosystem resources (RESOURCES.md)building blocks, designs, and partners gathered by the projectCVA6 Kanban boardplanned improvements tracked by the projectCVA6 SDKbuild a bootable Linux image (toolchain, OpenSBI, U-Boot, kernel)CVA6 dashboard (Thales CI)continuous-integration status linked from the README badgeCVA6 Tier CI Dashboardlatest status, coverage matrix, trends, and run history for the reference, Tier 1, and Tier 2 GitHub Actions workflowsFounding publication (Zaruba & Benini, IEEE TVLSI 2019)the citation recommended by the repository
3,133stars
1,031forks
Assemblyrepository language (GitHub)
Categories
Processor Cores
Tags
OpenHWRISC-VCoreEmbedded-classApplication-classArianeASICCPUFPGARV64GC
Suitable For
EngineerResearcherContributor
Architecture / Focus
Embedded-classApplication-class
Contribution ActivityHighly Active
216
Contributors
234
Open Issues
56
Recent Commits (4 weeks)
32
Open PRs
Data as of Sep 28, 2026
Knowledge Base
5 paper(s)
The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-Ready 1.7-GHz 64-Bit RISC-V Core in 22-nm FDSOI Technology
Florian Zaruba, Luca Benini
IEEE Transactions on VLSI Systems, 2019
View PaperOpenPiton+Ariane: The First Open-Source, SMP Linux-booting RISC-V System Scaling From One to Many Cores
Jonathan Balkind et al.
Computer Architecture Research with RISC-V Workshop (CARRV), 2019
View PaperCulsans: An Efficient Snoop-based Coherency Unit for the CVA6 Open Source RISC-V application processor
Riccardo Tedeschi et al.
arXiv preprint, 2024
View PaperCVA6-VMRT: A Modular Approach Towards Time-Predictable Virtual Memory in a 64-bit Application Class RISC-V Processor
Christopher Reinwardt et al.
arXiv preprint, 2025
View PaperOccamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET
Gianna Paulin, Paul Scheffler, Thomas Benz, et al.
2024 IEEE Symposium on VLSI Technology and Circuits, 2024
View PaperVerified adoption, contributor and lineage records, educational use, presentations, articles, and ecosystem data will be added incrementally from named sources.
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CV-X-IF (eXtension Interface)
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CV-MESH
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CVA6-Safe
CVA6-Safe is an experimental CVA6-based subsystem that can operate as a dual-core lockstep pair or as two independent cores. In lockstep mode it adds comparison-based fault detection and cache error detection/correction; split mode trades those protections for a regular dual-core asymmetric-multiprocessing setup. The project is relevant to engineers studying fault-tolerant RISC-V architectures, but the public design documentation is still incomplete and the repository does not claim an ISO 26262 certification.
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CVA6 SDK
CVA6 SDK is the Buildroot-based path for producing a complete bootable Linux image for CVA6 FPGA systems. A single build coordinates the RISC-V toolchain, OpenSBI, U-Boot and device tree, Linux kernel, initramfs, and root filesystem, then packages them into a flashable SD-card image. It is the practical starting point for users bringing up 32-bit or 64-bit CVA6 on Genesys 2 or Agilex 7; teams committed to Yocto should compare it with meta-cva6-yocto.