Back to ProjectsStart with GitHub
CVA6-Safe is an experimental CVA6-based subsystem that can operate as a dual-core lockstep pair or as two independent cores. In lockstep mode it adds comparison-based fault detection and cache error detection/correction; split mode trades those protections for a regular dual-core asymmetric-multiprocessing setup. The project is relevant to engineers studying fault-tolerant RISC-V architectures, but the public design documentation is still incomplete and the repository does not claim an ISO 26262 certification.
Start here
Category: SoC & SubsystemStatus: Editorial · ExperimentalBest for: Engineer
At a glance
- Architecture: dual-core lockstep subsystem built from CVA6 cores with cache error detection and correction
- Operating modes: lockstep or split/regular dual-core behavior selected at design time or power-on
- Protection boundary: cache EDAC is active in lockstep mode and disabled in split mode
- Demonstrated target: 32-bit CVA6 configuration with IMAC, Zicsr, and Sv32
- Maturity boundary: detailed public design documentation remains incomplete and no functional-safety certification is claimed
Further resources
2stars
5forks
SystemVerilogrepository language (GitHub)
Categories
SoC & Subsystem
Tags
OpenHWRISC-VSoCFault-tolerant / lockstepLockstepDCLSFault ToleranceEDACCVA6
Suitable For
EngineerResearcher
Architecture / Focus
Fault-tolerant / lockstep
Contribution ActivityLow Activity
3
Contributors
0
Open Issues
0
Recent Commits (4 weeks)
0
Open PRs
Data as of Sep 28, 2026
Verified adoption, contributor and lineage records, educational use, presentations, articles, and ecosystem data will be added incrementally from named sources.
Related Projects
CVA6
CVA6 is a configurable six-stage, in-order CORE-V processor family for 32-bit and 64-bit embedded and application-class systems. Its RTL includes both single-issue configurations, such as CV32A60X, and dual-issue configurations, such as CV32A65X. ISA extensions, privilege modes, and virtual memory depend on the selected configuration: application configurations can run Linux, while the embedded CV32A60X and CV32A65X configurations have no MMU or S/U modes. The repository brings together processor RTL, verification, FPGA integration, and documentation for engineers evaluating a core or exploring custom extensions through CV-X-IF.
CVA6 DCLS
cva6-dcls is an early-stage dual-core lockstep platform for CVA6. Its public repository confirms the DCLS scope and shows current development activity, but it does not yet publish enough architecture, configuration, safety-mechanism, or verification detail for an engineering evaluation. Readers can use it to follow emerging lockstep work; anyone selecting a design today should also examine CVA6-Safe, whose public subsystem behavior is documented in greater detail.
CV32E40S
CV32E40S is a compact four-stage, in-order 32-bit RISC-V core designed for security-oriented embedded systems. Building on the CV32E40P lineage, it adds Machine and User privilege modes, enhanced physical memory protection, anti-tampering mechanisms, and the Xsecure extension set. It is a relevant choice when evaluating protection-focused MCU designs; it should not be confused with the lockstep and fault-tolerance work in CVA6-Safe.