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CV32E40S is a compact four-stage, in-order 32-bit RISC-V core designed for security-oriented embedded systems. Building on the CV32E40P lineage, it adds Machine and User privilege modes, enhanced physical memory protection, anti-tampering mechanisms, and the Xsecure extension set. It is a relevant choice when evaluating protection-focused MCU designs; it should not be confused with the lockstep and fault-tolerance work in CVA6-Safe.
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Category: Processor CoresStatus: OpenHW · ActiveBest for: Engineer
At a glance
- Architecture: 32-bit, four-stage, in-order embedded-class RISC-V core
- ISA options: RV32I or RV32E, M or Zmmul, compressed and bit-manipulation extensions, and Xsecure
- Protection features: Machine and User modes, enhanced PMP, and anti-tampering mechanisms
- Origin: derived from CV32E40P and the earlier PULP RI5CY line
- Verification: core-specific UVM and formal work is maintained in cv32e40s-dv with shared infrastructure from core-v-verif
- Readiness: the family table describes a mature design with no active work toward its TRL goal; the organization's Active Development listing is not a TRL achievement or security certification
Further resources
CV32E40S User Manualofficial architecture, security, and integration documentationCV32E40S design-verification repositorycore-specific UVM and formal-verification directoriesCORE-V verification environmentshared functional-verification infrastructureCORE-V family overviewofficial family and maturity context
163stars
29forks
SystemVerilogrepository language (GitHub)
Categories
Processor Cores
Tags
OpenHWRISC-VCoreEmbedded-classSecurity-focusedSecurityPMPIoTSystemVerilog
Suitable For
EngineerResearcherContributor
Architecture / Focus
Embedded-classSecurity-focused
Contribution ActivityLow Activity
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Recent Commits (4 weeks)
2
Open PRs
Data as of Sep 28, 2026
Verified adoption, contributor and lineage records, educational use, presentations, articles, and ecosystem data will be added incrementally from named sources.
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CV32E40P is a compact four-stage, in-order 32-bit RISC-V core for embedded and MCU-class systems. It combines RV32IMC with optional floating-point support and PULP custom extensions aimed at code density, DSP-style performance, and energy efficiency. Its clear documentation, mature v1 release, and shared CORE-V verification flow make it useful both for learning a production-oriented embedded core and for integrating or extending a small CPU in an SoC.
CV32E40X
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CVA6-Safe
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