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CV32E40P is a compact four-stage, in-order 32-bit RISC-V core for embedded and MCU-class systems. It combines RV32IMC with optional floating-point support and PULP custom extensions aimed at code density, DSP-style performance, and energy efficiency. Its clear documentation, mature v1 release, and shared CORE-V verification flow make it useful both for learning a production-oriented embedded core and for integrating or extending a small CPU in an SoC.
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Category: Processor CoresStatus: Editorial · MatureBest for: Engineer
At a glance
- Architecture: 32-bit, four-stage, in-order embedded-class RISC-V core
- ISA: RV32IMC with optional F or Zfinx support and PULP custom extensions
- Origin: evolved from the RI5CY core developed by the PULP Platform team and moved to OpenHW in 2020
- Readiness: CV32E40Pv1 v1.0.0 achieved TRL-5 excluding F and XPULP verification; CV32E40Pv2 v1.8.3 has not yet reached its TRL-5 goal and does not inherit v1 verification coverage
- Verification boundary: production verification is maintained in core-v-verif; the simple RTL-repository testbench is for experimentation
Further resources
CV32E40P User Manualofficial architecture, interfaces, integration, and release documentationCORE-V family and release tabledevice variants, TRL status, and assigned architecture IDsCORE-V verification environmentshared functional-verification infrastructure used by CV32E40PRI5CY/CV32E40P founding paperpublished description cited by the project
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SystemVerilogrepository language (GitHub)
Categories
Processor Cores
Tags
OpenHWRISC-VCoreEmbedded-classLow PowerRV32IMFCRV32Embedded MCUPULPSystemVerilog
Suitable For
EngineerStudentResearcherContributor
Architecture / Focus
Embedded-classLow-power focus
Contribution ActivityLow Activity
40
Contributors
60
Open Issues
0
Recent Commits (4 weeks)
20
Open PRs
Data as of Sep 28, 2026
Knowledge Base
2 paper(s)
Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices
Michael Gautschi, Pasquale Davide Schiavone, Andreas Traber, et al.
IEEE Transactions on VLSI Systems, 2017
View PaperSlow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications
Pasquale Davide Schiavone, Francesco Conti, Davide Rossi, et al.
PATMOS, 2017
View PaperVerified adoption, contributor and lineage records, educational use, presentations, articles, and ecosystem data will be added incrementally from named sources.
Related Projects
CV32E40X
CV32E40X is a compact four-stage, in-order 32-bit RISC-V core for compute-oriented embedded systems. Its defining feature is CORE-V-XIF, which lets designers implement custom instructions in an external coprocessor without embedding that logic directly in the CPU pipeline. It is most relevant to engineers and researchers exploring domain-specific acceleration, but adopters should note that the core is considered mature while not currently progressing toward its TRL-5 target.
CV32E40S
CV32E40S is a compact four-stage, in-order 32-bit RISC-V core designed for security-oriented embedded systems. Building on the CV32E40P lineage, it adds Machine and User privilege modes, enhanced physical memory protection, anti-tampering mechanisms, and the Xsecure extension set. It is a relevant choice when evaluating protection-focused MCU designs; it should not be confused with the lockstep and fault-tolerance work in CVA6-Safe.
CORE-V MCU
CORE-V MCU is a standalone microcontroller-class SoC platform built around CV32E40P and derived from PULPissimo. The repository combines processor integration, memories, peripherals, FPGA targets, simulation flows, and JTAG debug into a complete system rather than providing another CPU core. It is a useful reference for engineers who want to see how a CORE-V core is assembled into an ASIC- or FPGA-oriented MCU, with Nexys A7 and Genesys 2 paths available for hands-on bring-up.
CORE-V Verification
core-v-verif is shared functional-verification infrastructure for CORE-V processors. It combines reusable UVM components, simulation Makefiles, verification libraries, utilities, vendor dependencies, and DV plans, with dedicated directories for CV32E40P, CV32E40X, and CV32E40S. Verification engineers can start with the common methodology and then select a core-specific flow. For CVA6, use the verif directory in the CVA6 repository: the current core-v-verif tree does not contain a CVA6-specific directory, although CVA6-related environments can reuse its shared components.