core-v-verif is shared functional-verification infrastructure for CORE-V processors. It combines reusable UVM components, simulation Makefiles, verification libraries, utilities, vendor dependencies, and DV plans, with dedicated directories for CV32E40P, CV32E40X, and CV32E40S. Verification engineers can start with the common methodology and then select a core-specific flow. For CVA6, use the verif directory in the CVA6 repository: the current core-v-verif tree does not contain a CVA6-specific directory, although CVA6-related environments can reuse its shared components.
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Verified adoption, contributor and lineage records, educational use, presentations, articles, and ecosystem data will be added incrementally from named sources.
CV32E40P is a compact four-stage, in-order 32-bit RISC-V core for embedded and MCU-class systems. It combines RV32IMC with optional floating-point support and PULP custom extensions aimed at code density, DSP-style performance, and energy efficiency. Its clear documentation, mature v1 release, and shared CORE-V verification flow make it useful both for learning a production-oriented embedded core and for integrating or extending a small CPU in an SoC.
CV32E40X is a compact four-stage, in-order 32-bit RISC-V core for compute-oriented embedded systems. Its defining feature is CORE-V-XIF, which lets designers implement custom instructions in an external coprocessor without embedding that logic directly in the CPU pipeline. It is most relevant to engineers and researchers exploring domain-specific acceleration, but adopters should note that the core is considered mature while not currently progressing toward its TRL-5 target.
CV32E40S is a compact four-stage, in-order 32-bit RISC-V core designed for security-oriented embedded systems. Building on the CV32E40P lineage, it adds Machine and User privilege modes, enhanced physical memory protection, anti-tampering mechanisms, and the Xsecure extension set. It is a relevant choice when evaluating protection-focused MCU designs; it should not be confused with the lockstep and fault-tolerance work in CVA6-Safe.
CVA6 is a configurable six-stage, in-order CORE-V processor family for 32-bit and 64-bit embedded and application-class systems. Its RTL includes both single-issue configurations, such as CV32A60X, and dual-issue configurations, such as CV32A65X. ISA extensions, privilege modes, and virtual memory depend on the selected configuration: application configurations can run Linux, while the embedded CV32A60X and CV32A65X configurations have no MMU or S/U modes. The repository brings together processor RTL, verification, FPGA integration, and documentation for engineers evaluating a core or exploring custom extensions through CV-X-IF.