Back to ProjectsStart with GitHub
CV32E40X is a compact four-stage, in-order 32-bit RISC-V core for compute-oriented embedded systems. Its defining feature is CORE-V-XIF, which lets designers implement custom instructions in an external coprocessor without embedding that logic directly in the CPU pipeline. It is most relevant to engineers and researchers exploring domain-specific acceleration, but adopters should note that the core is considered mature while not currently progressing toward its TRL-5 target.
Start here
Category: Processor CoresStatus: OpenHW · MatureBest for: Engineer
At a glance
- Architecture: 32-bit, four-stage, in-order embedded-class RISC-V core
- ISA options: RV32I or RV32E, M or Zmmul, compressed and bit-manipulation extensions, plus optional atomic support
- Extension path: CORE-V-XIF offloads custom instructions to an external coprocessor
- Origin: derived from CV32E40P and the earlier PULP RI5CY line
- Readiness: mature implementation, but not in active development toward its TRL goal and not yet at TRL-5
Further resources
CV32E40X User Manualofficial core architecture and interface documentationCORE-V-XIF specificationextension-interface contract used by the coreCORE-V verification environmentshared verification infrastructure referenced by the RTL repositoryCV32E40X design-verification repositorycore-specific UVM and formal-verification material
281stars
75forks
SystemVerilogrepository language (GitHub)
Categories
Processor Cores
Tags
OpenHWRISC-VCoreEmbedded-classCompute ExtensionsX-InterfaceCoprocessorSystemVerilogCustom Extensions
Suitable For
EngineerResearcherContributor
Architecture / Focus
Embedded-class
Contribution ActivityLow Activity
43
Contributors
38
Open Issues
0
Recent Commits (4 weeks)
8
Open PRs
Data as of Sep 28, 2026
Verified adoption, contributor and lineage records, educational use, presentations, articles, and ecosystem data will be added incrementally from named sources.
Related Projects
CV32E40P
CV32E40P is a compact four-stage, in-order 32-bit RISC-V core for embedded and MCU-class systems. It combines RV32IMC with optional floating-point support and PULP custom extensions aimed at code density, DSP-style performance, and energy efficiency. Its clear documentation, mature v1 release, and shared CORE-V verification flow make it useful both for learning a production-oriented embedded core and for integrating or extending a small CPU in an SoC.
CV32E40S
CV32E40S is a compact four-stage, in-order 32-bit RISC-V core designed for security-oriented embedded systems. Building on the CV32E40P lineage, it adds Machine and User privilege modes, enhanced physical memory protection, anti-tampering mechanisms, and the Xsecure extension set. It is a relevant choice when evaluating protection-focused MCU designs; it should not be confused with the lockstep and fault-tolerance work in CVA6-Safe.
CV32E40X Design Verification
cv32e40x-dv is the core-specific design-verification environment for CV32E40X. It separates software-test compilation, UVM infrastructure, simulation, top-level testbench code, test cases, and formal-verification runs, giving engineers a direct map from an RTL change to the relevant verification area. Use it together with the CV32E40X RTL repository and shared core-v-verif components when validating the core or its custom-extension interface.
CORE-V Verification
core-v-verif is shared functional-verification infrastructure for CORE-V processors. It combines reusable UVM components, simulation Makefiles, verification libraries, utilities, vendor dependencies, and DV plans, with dedicated directories for CV32E40P, CV32E40X, and CV32E40S. Verification engineers can start with the common methodology and then select a core-specific flow. For CVA6, use the verif directory in the CVA6 repository: the current core-v-verif tree does not contain a CVA6-specific directory, although CVA6-related environments can reuse its shared components.