Back to ProjectsStart with GitHub
cv32e40x-dv is the core-specific design-verification environment for CV32E40X. It separates software-test compilation, UVM infrastructure, simulation, top-level testbench code, test cases, and formal-verification runs, giving engineers a direct map from an RTL change to the relevant verification area. Use it together with the CV32E40X RTL repository and shared core-v-verif components when validating the core or its custom-extension interface.
Start here
Category: VerificationStatus: Editorial · ActiveBest for: Engineer
At a glance
- Target: design-verification environment for the CV32E40X core
- BSP: compiles, assembles, and links core test programs
- UVM structure: environment class and supporting infrastructure live under env
- Flow separation: simulation, top-level testbench code, test cases, and formal work have dedicated directories
- Integration context: shared verification components are supplied through the CORE-V verification ecosystem
Further resources
19stars
11forks
Assemblyrepository language (GitHub)
Categories
Verification
Tags
OpenHWRISC-VVerificationUVM TestbenchFormal VerificationCore DVFormalAssemblyDV
Suitable For
EngineerContributor
Verification Type
UVM TestbenchFormal Verification
Contribution ActivityLow Activity
18
Contributors
4
Open Issues
0
Recent Commits (4 weeks)
1
Open PRs
Data as of Sep 28, 2026
Verified adoption, contributor and lineage records, educational use, presentations, articles, and ecosystem data will be added incrementally from named sources.
Related Projects
CV32E40X
CV32E40X is a compact four-stage, in-order 32-bit RISC-V core for compute-oriented embedded systems. Its defining feature is CORE-V-XIF, which lets designers implement custom instructions in an external coprocessor without embedding that logic directly in the CPU pipeline. It is most relevant to engineers and researchers exploring domain-specific acceleration, but adopters should note that the core is considered mature while not currently progressing toward its TRL-5 target.
CORE-V Verification
core-v-verif is shared functional-verification infrastructure for CORE-V processors. It combines reusable UVM components, simulation Makefiles, verification libraries, utilities, vendor dependencies, and DV plans, with dedicated directories for CV32E40P, CV32E40X, and CV32E40S. Verification engineers can start with the common methodology and then select a core-specific flow. For CVA6, use the verif directory in the CVA6 repository: the current core-v-verif tree does not contain a CVA6-specific directory, although CVA6-related environments can reuse its shared components.