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CORE-V MCU is a standalone microcontroller-class SoC platform built around CV32E40P and derived from PULPissimo. The repository combines processor integration, memories, peripherals, FPGA targets, simulation flows, and JTAG debug into a complete system rather than providing another CPU core. It is a useful reference for engineers who want to see how a CORE-V core is assembled into an ASIC- or FPGA-oriented MCU, with Nexys A7 and Genesys 2 paths available for hands-on bring-up.
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Category: SoC & SubsystemStatus: Editorial · ActiveBest for: Student
At a glance
- Origin: derived from PULPissimo and maintained as an independent OpenHW project
- Processor: ASIC- and FPGA-oriented MCU implementation built around CV32E40P
- FPGA flows: pre-built Nexys A7 quick start plus build targets for Nexys A7 and Genesys 2
- Tooling: Make, FuseSoC, Verilator, Vivado, and a Questa simulation target
- Debug: IEEE 1149.1 JTAG Test Access Port with a RISC-V Debug Transport Module
- Research context: the Quentin and Arnold papers describe related predecessor designs, not production qualification or measured performance of the current CORE-V MCU revision
Further resources
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79forks
SystemVerilogrepository language (GitHub)
Categories
SoC & Subsystem
Tags
OpenHWRISC-VSoCMicrocontrollerOpenhwgroupSystemVerilogReference SoCPeripheral IntegrationFPGAEmbedded
Suitable For
StudentEngineerContributor
Contribution ActivityLow Activity
20
Contributors
75
Open Issues
1
Recent Commits (4 weeks)
9
Open PRs
Data as of Sep 28, 2026
Knowledge Base
2 paper(s)
Quentin: an Ultra-Low-Power PULPissimo SoC in 22nm FDX
Pasquale Davide Schiavone, Davide Rossi, Antonio Pullini, et al.
IEEE S3S, 2018
View PaperArnold: An eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End Nodes
Pasquale Davide Schiavone, Davide Rossi, Alfio Di Mauro, et al.
IEEE Transactions on VLSI Systems, 2021
View PaperVerified adoption, contributor and lineage records, educational use, presentations, articles, and ecosystem data will be added incrementally from named sources.
Related Projects
CV32E40P
CV32E40P is a compact four-stage, in-order 32-bit RISC-V core for embedded and MCU-class systems. It combines RV32IMC with optional floating-point support and PULP custom extensions aimed at code density, DSP-style performance, and energy efficiency. Its clear documentation, mature v1 release, and shared CORE-V verification flow make it useful both for learning a production-oriented embedded core and for integrating or extending a small CPU in an SoC.
CORE-V MCU DevKit
CORE-V MCU DevKit contains the hardware-design artifacts for an evaluation board built around CORE-V MCU and the CV32E40P v1.0.0 core. The board combines a QuickLogic ArcticPro2 embedded FPGA, flash, on-board JTAG/debug, expansion and sensor interfaces, camera support, and AWS IoT ExpressLink connectivity; the repository provides KiCad sources and schematics rather than processor RTL. It is most useful to board designers and bring-up engineers who need a concrete hardware platform for the CORE-V MCU ecosystem.
CORE-V MCU UVM
core-v-mcu-uvm is the chip- and subsystem-level UVM environment built to raise the verification maturity of CORE-V MCU toward TRL-5 and beyond. It covers the MCU at chip level and includes reusable environments for blocks such as the APB timer, while consuming the RTL as a submodule. This repository is most relevant to experienced DV engineers because its flows depend on Moore.io packages, simulator-specific tooling, and in some cases licensed Datum verification IP; the stated TRL level is a goal, not an achieved certification.