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core-v-mcu-uvm is the chip- and subsystem-level UVM environment built to raise the verification maturity of CORE-V MCU toward TRL-5 and beyond. It covers the MCU at chip level and includes reusable environments for blocks such as the APB timer, while consuming the RTL as a submodule. This repository is most relevant to experienced DV engineers because its flows depend on Moore.io packages, simulator-specific tooling, and in some cases licensed Datum verification IP; the stated TRL level is a goal, not an achieved certification.
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Category: VerificationStatus: Editorial · Low activityBest for: Engineer
At a glance
- Goal: advance CORE-V MCU verification toward TRL-5 and beyond; this is a target rather than a completed milestone
- Scope: chip-level CORE-V MCU environment and testbench plus APB timer subsystem environments
- RTL boundary: CORE-V MCU is consumed as a Git submodule and is not maintained here
- Tooling: Moore.io packages, Metrics DSim Cloud, Vivado, and simulator-specific flows
- Access requirements: some VIP libraries require a Moore.io account and licensed Datum packages
Further resources
29stars
9forks
SystemVerilogrepository language (GitHub)
Categories
Verification
Tags
OpenHWRISC-VVerificationUVM TestbenchSoC VerificationUVMSystemVerilogMCU
Suitable For
Engineer
Verification Type
UVM Testbench
Contribution ActivityLow Activity
2
Contributors
17
Open Issues
0
Recent Commits (4 weeks)
0
Open PRs
Data as of Sep 28, 2026
Verified adoption, contributor and lineage records, educational use, presentations, articles, and ecosystem data will be added incrementally from named sources.
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