cva6-dcls is an early-stage dual-core lockstep platform for CVA6. Its public repository confirms the DCLS scope and shows current development activity, but it does not yet publish enough architecture, configuration, safety-mechanism, or verification detail for an engineering evaluation. Readers can use it to follow emerging lockstep work; anyone selecting a design today should also examine CVA6-Safe, whose public subsystem behavior is documented in greater detail.
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CVA6 is a configurable six-stage, in-order CORE-V processor family for 32-bit and 64-bit embedded and application-class systems. Its RTL includes both single-issue configurations, such as CV32A60X, and dual-issue configurations, such as CV32A65X. ISA extensions, privilege modes, and virtual memory depend on the selected configuration: application configurations can run Linux, while the embedded CV32A60X and CV32A65X configurations have no MMU or S/U modes. The repository brings together processor RTL, verification, FPGA integration, and documentation for engineers evaluating a core or exploring custom extensions through CV-X-IF.
CVA6-Safe is an experimental CVA6-based subsystem that can operate as a dual-core lockstep pair or as two independent cores. In lockstep mode it adds comparison-based fault detection and cache error detection/correction; split mode trades those protections for a regular dual-core asymmetric-multiprocessing setup. The project is relevant to engineers studying fault-tolerant RISC-V architectures, but the public design documentation is still incomplete and the repository does not claim an ISO 26262 certification.