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CVA6 DCLS

ExperimentalOpenHW Explorer editorial assessment

cva6-dcls is an early-stage dual-core lockstep platform for CVA6. Its public repository confirms the DCLS scope and shows current development activity, but it does not yet publish enough architecture, configuration, safety-mechanism, or verification detail for an engineering evaluation. Readers can use it to follow emerging lockstep work; anyone selecting a design today should also examine CVA6-Safe, whose public subsystem behavior is documented in greater detail.

Reviewed profileOfficial sourcesVerified 2026-07-164 sourcesPrimary source
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Category: SoC & SubsystemStatus: Editorial · ExperimentalBest for: Engineer
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At a glance

  • Confirmed scope: dual-core lockstep module/platform for the CVA6 processor core
  • Documentation state: public project documentation is still marked under construction
  • Evidence limit: detailed architecture, safety mechanisms, configuration options, and verification results are not yet public
  • Activity context: development continued in 2026, but activity alone does not establish technical maturity

Further resources

CVA6 repositoryprocessor core named by the projectCVA6-Saferelated repository with publicly documented lockstep and split-mode behaviorCVA6 User Manualofficial documentation for the underlying processor core
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Categories

SoC & Subsystem

Tags

OpenHWRISC-VSoCLockstepSafetyDCLSCVA6

Suitable For

EngineerResearcher

Contribution ActivityLow Activity

1

Contributors

3

Open Issues

0

Recent Commits (4 weeks)

0

Open PRs

Data as of Sep 28, 2026

Verified adoption, contributor and lineage records, educational use, presentations, articles, and ecosystem data will be added incrementally from named sources.

Related Projects

CVA6

CVA6 is a configurable six-stage, in-order CORE-V processor family for 32-bit and 64-bit embedded and application-class systems. Its RTL includes both single-issue configurations, such as CV32A60X, and dual-issue configurations, such as CV32A65X. ISA extensions, privilege modes, and virtual memory depend on the selected configuration: application configurations can run Linux, while the embedded CV32A60X and CV32A65X configurations have no MMU or S/U modes. The repository brings together processor RTL, verification, FPGA integration, and documentation for engineers evaluating a core or exploring custom extensions through CV-X-IF.

CVA6-Safe

CVA6-Safe is an experimental CVA6-based subsystem that can operate as a dual-core lockstep pair or as two independent cores. In lockstep mode it adds comparison-based fault detection and cache error detection/correction; split mode trades those protections for a regular dual-core asymmetric-multiprocessing setup. The project is relevant to engineers studying fault-tolerant RISC-V architectures, but the public design documentation is still incomplete and the repository does not claim an ISO 26262 certification.

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