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CV-MESH is an early-stage OpenHW repository for cache-coherence and interconnect components derived from the OpenPiton context. Its public tree contains bridges, L1.5 and L2 cache logic, and network-on-chip blocks, and related OpenHW platforms use CV-MESH in multicore integration work. Public top-level documentation is still missing, so the repository is suitable mainly for experienced engineers tracing existing RTL; topology, supported scale, protocol details, and maturity cannot yet be assessed from a stable public specification.
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Category: IP ComponentsStatus: Editorial · ExperimentalBest for: Researcher
At a glance
- Positioning: cache-coherence framework associated with OpenPiton
- Public tree: bridges, include, l15, l2, and noc directories
- Documentation limit: no top-level project introduction or stable public specification
- Evidence limit: topology, protocol, supported scale, and maturity are not publicly established
- Related platforms: CVA6 Platform and CORE-V Polara APU provide OpenPiton/CV-MESH integration context
Further resources
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Verilogrepository language (GitHub)
Categories
IP Components
Tags
OpenHWRISC-VIPNoCInterconnectMeshMulti-CoreVerilog
Suitable For
Researcher
Contribution ActivityLow Activity
8
Contributors
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Open Issues
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Recent Commits (4 weeks)
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Open PRs
Data as of Sep 28, 2026
Knowledge Base
1 paper(s)
OpenPiton: An Open Source Manycore Research Framework
J. Balkind et al.
ASPLOS (ACM International Conference on Architectural Support for Programming Languages and Operating Systems), 2016
View PaperVerified adoption, contributor and lineage records, educational use, presentations, articles, and ecosystem data will be added incrementally from named sources.
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