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CORE-V Polara APU is a multicore vector-processing research platform that combines ideas and code from Ara with the OpenPiton manycore infrastructure. Its documented configuration connects four RISC-V vector cores and includes low-precision operations relevant to DNN inference. The repository is aimed at researchers evaluating vector and multicore systems; reproducing its flows requires a vector-capable RISC-V LLVM toolchain and supported commercial simulators.
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Category: SoC & SubsystemStatus: Editorial · ExperimentalBest for: Researcher
At a glance
- Version boundary: integration depends on the Ara and platform revisions pinned by this repository; newer upstream Ara or RVV capabilities do not automatically apply
- Origin: combines the PULP Ara vector processor with Princeton OpenPiton infrastructure
- Topology: four RISC-V vector cores connected through OpenPiton
- Compute scope: includes low-precision operations for DNN inference
- Toolchain: requires a RISC-V LLVM compiler with vector-extension support
- Simulation: VCS and ModelSim/QuestaSim flows depend on external commercial tools
Further resources
17stars
7forks
Assemblyrepository language (GitHub)
Categories
SoC & Subsystem
Tags
OpenHWRISC-VSoCOpenPitonMulti-CoreAPUHPCResearch
Suitable For
Researcher
Contribution ActivityLow Activity
16
Contributors
0
Open Issues
0
Recent Commits (4 weeks)
3
Open PRs
Data as of Sep 28, 2026
Knowledge Base
2 paper(s)
Ara: A 1-GHz+ Scalable and Energy-Efficient RISC-V Vector Processor With Multiprecision Floating-Point Support in 22-nm FD-SOI
Matheus Cavalcante et al.
IEEE Transactions on VLSI Systems, 2019
View PaperOpenPiton: An Open Source Manycore Research Framework
J. Balkind, M. McKeown, Y. Fu et al.
ASPLOS, 2016
View PaperVerified adoption, contributor and lineage records, educational use, presentations, articles, and ecosystem data will be added incrementally from named sources.
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