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CV-X-IF, the CORE-V eXtension Interface, specifies how custom coprocessors and instruction-set extensions connect to a RISC-V CPU. Its basic channels handle compressed instructions, instruction issue, register operands, commit control, and results, allowing accelerator logic to remain outside the host pipeline. Memory and memory-result channels are optional and depend on the specification version and processor implementation. Integrators should check both sides of the interface against the same supported protocol; this is an interface specification, not a ready-made accelerator or a general mechanism for arbitrary control-flow and privileged extensions.
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Category: IP ComponentsStatus: Editorial · ActiveBest for: Engineer
At a glance
- Artifact type: versioned interface specification, not a processor core or concrete accelerator
- Purpose: connect custom coprocessors and ISA extensions to an existing RISC-V processor
- Protocol structure: compressed, issue, register, commit, and result channels; memory and memory-result channels are optional and implementation-dependent
- Documentation: reStructuredText/Sphinx sources published through OpenHW documentation hosting
- Versioning: semantic versions derived from Git tags through setuptools_scm
Further resources
96stars
31forks
SystemVerilogrepository language (GitHub)
Categories
IP ComponentsDocumentation
Tags
OpenHWRISC-VIPDocumentationExtension InterfaceCoprocessorExtensionInterfaceSystemVerilogAccelerator
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Contribution ActivityLow Activity
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Data as of Sep 28, 2026
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