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CV-HPDCache is a configurable, high-performance L1 data-cache controller for RISC-V cores and accelerators. Its multi-requester, non-blocking architecture can keep multiple reads and writes in flight, execute non-overlapping accesses out of order, and support write-through or write-back policies together with RISC-V cache-management and atomic operations. It is aimed at SoC and microarchitecture engineers who need reusable cache IP; CVA6 provides a concrete integration path, while verification limitations should be reviewed in the separate cv-hpdcache-verif project.
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Category: IP ComponentsStatus: Editorial · ActiveBest for: Engineer
At a glance
- Role: SystemVerilog L1 data-cache IP for RISC-V cores and accelerators
- Request model: multiple requesters and multiple outstanding read/write transactions
- Ordering: overlapping-address requests commit in consumption order; non-overlapping requests may execute out of order
- Policies and ISA support: non-allocate write-through, allocate write-back, RISC-V CMOs, AMOs, and RVWMO
- Integration: CVA6 can select HPDcache through its DCacheType configuration
Further resources
SystemC/Verilator testbenchstandalone testbench in the RTL repository, separate from the dedicated UVM projectCV-HPDCache User Guideofficial architecture and integration documentationCV-HPDCache verificationdedicated UVM subsystem environmentCVA6 integration exampleconcrete integration referenced by the READMEOriginal HPDcache publicationpublication listed by the project
119stars
57forks
SystemVerilogrepository language (GitHub)
Categories
IP Components
Tags
OpenHWRISC-VIPL1 D-CacheNon-BlockingCacheL1High PerformanceSystemVerilog
Suitable For
EngineerResearcherContributor
Contribution ActivityModerately Active
17
Contributors
3
Open Issues
4
Recent Commits (4 weeks)
4
Open PRs
Data as of Sep 28, 2026
Knowledge Base
2 paper(s)
HPDcache: Open-Source High-Performance L1 Data Cache for RISC-V Cores
Cesar Fuguet
ACM Computing Frontiers, 2023
View PaperBreaking the Memory Wall with a Flexible Open-Source L1 Data-Cache
D. Million, N. Oliete-Escuin, C. Fuguet
DATE, 2024
View PaperVerified adoption, contributor and lineage records, educational use, presentations, articles, and ecosystem data will be added incrementally from named sources.
Related Projects
CVA6
CVA6 is a configurable six-stage, in-order CORE-V processor family for 32-bit and 64-bit embedded and application-class systems. Its RTL includes both single-issue configurations, such as CV32A60X, and dual-issue configurations, such as CV32A65X. ISA extensions, privilege modes, and virtual memory depend on the selected configuration: application configurations can run Linux, while the embedded CV32A60X and CV32A65X configurations have no MMU or S/U modes. The repository brings together processor RTL, verification, FPGA integration, and documentation for engineers evaluating a core or exploring custom extensions through CV-X-IF.
CV-HPDCache Verification
cv-hpdcache-verif is the dedicated verification environment for the CV-HPDCache subsystem, covering the cache controller and prefetcher through Python-driven compile, test, and regression flows. It is useful for engineers working on cache correctness and subsystem integration, but it is not currently a turnkey verification baseline: only CFG1 is documented as working, the SystemVerilog PLRU model is disabled, and the optional AXI5 adapter remains unverified. The cache RTL itself is maintained separately in cv-hpdcache.