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cv-hpdcache-verif is the dedicated verification environment for the CV-HPDCache subsystem, covering the cache controller and prefetcher through Python-driven compile, test, and regression flows. It is useful for engineers working on cache correctness and subsystem integration, but it is not currently a turnkey verification baseline: only CFG1 is documented as working, the SystemVerilog PLRU model is disabled, and the optional AXI5 adapter remains unverified. The cache RTL itself is maintained separately in cv-hpdcache.
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Category: VerificationStatus: Editorial · ActiveBest for: Engineer
At a glance
- Verification target: HPDcache subsystem containing cache-controller and prefetcher DUTs
- Workflow: Python scripts compile RTL and UVM code, run individual tests, and launch parallel regressions
- Current working configuration: CFG1 is the only configuration identified as working
- Known gaps: the SystemVerilog PLRU model is disabled and the optional AXI5 adapter is not verified
- RTL boundary: cache implementation is maintained in the separate cv-hpdcache repository
Further resources
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10forks
SystemVerilogrepository language (GitHub)
Categories
Verification
Tags
OpenHWRISC-VVerificationUVM TestbenchCache VerificationUVMSystemVerilogCacheHPDCache
Suitable For
EngineerResearcherContributor
Verification Type
UVM Testbench
Contribution ActivityLow Activity
4
Contributors
0
Open Issues
0
Recent Commits (4 weeks)
1
Open PRs
Data as of Sep 28, 2026
Verified adoption, contributor and lineage records, educational use, presentations, articles, and ecosystem data will be added incrementally from named sources.
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