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CVFPU, also known as FPnew, is a parameterized SystemVerilog floating-point unit for processors and accelerators. Its built-in formats are FP32, FP64, FP16, FP8, and FP16ALT, with configurable operations, pipeline behavior, and optional packed SIMD. Other exponent and mantissa widths require extending the format definitions and checking the affected operations and verification coverage; binary128 is not a built-in selectable format. The design serves both conventional RISC-V floating point and transprecision research. It targets IEEE 754-2008 behavior, with documented rounding and inexact-flag limitations in the optional PULP DivSqrt implementation.
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Category: IP ComponentsStatus: Editorial · ActiveBest for: Engineer
At a glance
- Design: parameterized SystemVerilog floating-point unit also known as FPnew
- Built-in formats: FP32, FP64, FP16, FP8, and FP16ALT; additional formats require changes to the package definitions and corresponding verification
- Operations: arithmetic, fused multiply-add, division, square root, comparisons, conversions, classification, and optional packed SIMD
- Standards posture: designed to target IEEE 754-2008 behavior, without an unconditional compliance claim
- Known limitation: the PULP DivSqrt option has rounding and inexact-flag issues in some cases
Further resources
FPnew architecture documentationconfiguration, interfaces, and architectureCVFPU UVM environmentdedicated UVM verification projectFPnew publicationpublication recommended by the repositoryFPnew preprintopen-access version of the same FPnew work, not a separate paperCVA6 repositoryone OpenHW integration context for CVFPU
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SystemVerilogrepository language (GitHub)
Categories
IP Components
Tags
OpenHWRISC-VIPFloating PointTransprecisionFPUIEEE 754SystemVerilogParametric
Suitable For
EngineerResearcherContributor
Contribution ActivityLow Activity
25
Contributors
44
Open Issues
2
Recent Commits (4 weeks)
9
Open PRs
Data as of Sep 28, 2026
Knowledge Base
1 paper(s)
FPnew: An Open-Source Multiformat Floating-Point Unit Architecture for Energy-Proportional Transprecision Computing
Stefan Mach, Fabian Schuiki, Florian Zaruba, Luca Benini
IEEE Transactions on VLSI Systems, 2021
View PaperVerified adoption, contributor and lineage records, educational use, presentations, articles, and ecosystem data will be added incrementally from named sources.
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