OpenHW Explorer
ExploreLearning HubResourcesNewsAbout
GitHub
HomeProjectsCVFPU UVM Verification
Back to Projects

CVFPU UVM Verification

ActiveOpenHW Explorer editorial assessment

cvfpu-uvm is the dedicated UVM environment for verifying CVFPU through the floating-point wrapper used by CVA6. It combines test plans, agents, scoreboards, regression lists, and a C++ reference model connected to SystemVerilog through DPI, with CVA6 and core-v-verif supplied as dependencies. This repository is the right entry point for engineers validating floating-point operations and wrapper integration, provided they have access to one of the documented commercial simulator flows.

Reviewed profileOfficial sourcesVerified 2026-09-126 sourcesPrimary source
5 more sources
Source 2Source 3Source 4Source 5Source 6

Start here

Category: VerificationStatus: Editorial · ActiveBest for: Engineer
Start with GitHub

At a glance

  • DUT: CVA6 wrapper around the CVFPU floating-point unit
  • Testbench: UVM environment, agent, scoreboard, tests, top-level testbench, and regression lists
  • Reference model: C++ shared library connected to SystemVerilog through DPI
  • Dependencies: CVA6 and core-v-verif are included as Git submodules
  • Simulator support: documented flows for QuestaSim, Xcelium, and VCS
  • Coverage boundary: CVA6 wrapper only, no vector FP testing; RMM/ROD/DYN are not fully verified, formats beyond FP32/64/16 are tested only for F2F, and F2I/I2F covers INT32/64 only; some regressions expose known DUT bugs

Further resources

Known verification limitationssupported formats, rounding modes, conversions, and known DUT issues at the reviewed revisionCVFPU RTL repositoryfloating-point unit being verifiedCVFPU UVM test planverification planning materialCVA6 repositorysource of the wrapper used as the DUTCORE-V verification environmentshared dependency used by the testbench
24stars
12forks
Perlrepository language (GitHub)
View on GitHub

Categories

Verification

Tags

OpenHWRISC-VVerificationUVM TestbenchIEEE 754FPU VerificationUVMFPUFloating Point

Suitable For

EngineerResearcherContributor

Verification Type

UVM Testbench

Contribution ActivityLow Activity

4

Contributors

1

Open Issues

0

Recent Commits (4 weeks)

1

Open PRs

Data as of Sep 28, 2026

Verified adoption, contributor and lineage records, educational use, presentations, articles, and ecosystem data will be added incrementally from named sources.

Related Projects

CVFPU

CVFPU, also known as FPnew, is a parameterized SystemVerilog floating-point unit for processors and accelerators. Its built-in formats are FP32, FP64, FP16, FP8, and FP16ALT, with configurable operations, pipeline behavior, and optional packed SIMD. Other exponent and mantissa widths require extending the format definitions and checking the affected operations and verification coverage; binary128 is not a built-in selectable format. The design serves both conventional RISC-V floating point and transprecision research. It targets IEEE 754-2008 behavior, with documented rounding and inexact-flag limitations in the optional PULP DivSqrt implementation.

CVA6

CVA6 is a configurable six-stage, in-order CORE-V processor family for 32-bit and 64-bit embedded and application-class systems. Its RTL includes both single-issue configurations, such as CV32A60X, and dual-issue configurations, such as CV32A65X. ISA extensions, privilege modes, and virtual memory depend on the selected configuration: application configurations can run Linux, while the embedded CV32A60X and CV32A65X configurations have no MMU or S/U modes. The repository brings together processor RTL, verification, FPGA integration, and documentation for engineers evaluating a core or exploring custom extensions through CV-X-IF.

OpenHW Explorer
LicensingProject GitHubFeedback ↗OpenHW GitHubOpenHW Foundation websiteDocumentation
Alex ChenLinkedIn

OpenHW Explorer is an independent community project and is not an official OpenHW Foundation website.