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FORCE-RISCV

Low activityOpenHW Explorer editorial assessment

FORCE-RISCV is an instruction-sequence generator for stressing RISC-V processor implementations with large, controllable test programs. It randomizes instructions, registers, addresses, and data while allowing Python templates to constrain generation, control privilege transitions, and shape multi-process or multi-thread scenarios. The generated ELF and assembly outputs can feed RTL simulation, while Handcar provides a Spike-based reference path, making FORCE-RISCV useful to verification engineers who need broader stimulus than hand-written directed tests.

Reviewed profileOfficial sourcesVerified 2026-07-165 sourcesPrimary source
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Category: VerificationStatus: Editorial · Low activityBest for: Engineer
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At a glance

  • Purpose: constrained-random instruction-sequence generation for RISC-V processor verification
  • Generation model: randomizes instructions, registers, addresses, and data under user-supplied constraints
  • Test authoring: Python templates call FORCE-RISCV APIs to shape scenarios and execution modes
  • Outputs: executable ELF files and disassembled assembly files for RTL simulation and inspection
  • Reference path: Handcar integration is based on the Spike RISC-V instruction simulator

Further resources

FORCE-RISCV User Manual v0.8project-supplied user manualFORCE-RISCV quick startbuild, smoke-test, and test-generation workflowCORE-V verification environmentenvironment referenced for consuming generated tests
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Categories

VerificationTools & SDKs

Tags

OpenHWRISC-VVerificationToolsTest GenerationConstrained RandomPythonC++

Suitable For

EngineerResearcher

Verification Type

Test Generation

Contribution ActivityLow Activity

13

Contributors

18

Open Issues

0

Recent Commits (4 weeks)

2

Open PRs

Data as of Sep 28, 2026

Verified adoption, contributor and lineage records, educational use, presentations, articles, and ecosystem data will be added incrementally from named sources.

Related Projects

CORE-V Verification

core-v-verif is shared functional-verification infrastructure for CORE-V processors. It combines reusable UVM components, simulation Makefiles, verification libraries, utilities, vendor dependencies, and DV plans, with dedicated directories for CV32E40P, CV32E40X, and CV32E40S. Verification engineers can start with the common methodology and then select a core-specific flow. For CVA6, use the verif directory in the CVA6 repository: the current core-v-verif tree does not contain a CVA6-specific directory, although CVA6-related environments can reuse its shared components.

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