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CV32E41P is an archived four-stage, in-order 32-bit RISC-V prototype derived from CV32E40P. It was created to explore Zfinx and Zce extension work alongside Xpulp custom extensions, and OpenHW records it as a TRL-3 proof of concept rather than a production target. The repository remains valuable for historical implementation study, but new product work should begin with an actively maintained CORE-V core instead.
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Category: Processor CoresStatus: GitHub · ArchivedBest for: Researcher
At a glance
- Architecture: 32-bit, four-stage, in-order RISC-V core
- ISA focus: RV32IM with optional F or Zfinx, compressed/Zce work, and Xpulp custom extensions
- Purpose: prototype implementation used to explore Zfinx and Zce
- Readiness: completed at TRL-3 as a proof of concept, not intended for a production device
- Repository status: archived on GitHub
Further resources
27stars
10forks
SystemVerilogrepository language (GitHub)
Categories
Processor Cores
Tags
OpenHWRISC-VCoreEmbedded-classArchivedPrototypeSystemVerilogZfinxZce
Suitable For
Researcher
Architecture / Focus
Embedded-class
Contribution ActivityLow Activity
35
Contributors
9
Open Issues
0
Recent Commits (4 weeks)
2
Open PRs
Data as of Sep 28, 2026
Verified adoption, contributor and lineage records, educational use, presentations, articles, and ecosystem data will be added incrementally from named sources.
Related Projects
CV32E40P
CV32E40P is a compact four-stage, in-order 32-bit RISC-V core for embedded and MCU-class systems. It combines RV32IMC with optional floating-point support and PULP custom extensions aimed at code density, DSP-style performance, and energy efficiency. Its clear documentation, mature v1 release, and shared CORE-V verification flow make it useful both for learning a production-oriented embedded core and for integrating or extending a small CPU in an SoC.
CV32E40S
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