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CVA5 is a configurable 32-bit RISC-V soft processor designed specifically for FPGA implementation. Derived from Simon Fraser University's Taiga project, it supports RV32IMAFD and uses parallel, variable-latency execution units so new functional units can be added without forcing every operation into one fixed latency. It is best suited to FPGA architecture research and custom processor prototyping; its completed TRL-3 status means it should be evaluated as a research-ready platform rather than a currently advancing production core.
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Category: Processor CoresStatus: OpenHW · CompletedBest for: Engineer
At a glance
- Target: 32-bit RISC-V soft processor optimized for FPGA implementations
- ISA: the core repository supports RV32IMAFD; a shorter family overview lists RV32IMA, so the core repository is the more detailed implementation reference
- Implementation: extensible and highly configurable SystemVerilog RTL
- Microarchitecture: parallel, variable-latency execution units with support for adding new units
- Origin and readiness: derived from the Taiga project and completed at OpenHW TRL-3
Further resources
139stars
36forks
SystemVerilogrepository language (GitHub)
Categories
Processor Cores
Tags
OpenHWRISC-VCoreApplication-classFPGAApplication CoreSystemVerilogApplication-ClassPipeline
Suitable For
EngineerResearcher
Architecture / Focus
Application-class
Contribution ActivityLow Activity
9
Contributors
4
Open Issues
0
Recent Commits (4 weeks)
0
Open PRs
Data as of Sep 28, 2026
Knowledge Base
2 paper(s)
Designing an IEEE-Compliant FPU that Supports Configurable Precision for Soft Processors
Chris Keilbart et al.
ACM Transactions on Reconfigurable Technology and Systems, 2024
View PaperRethinking Integer Divider Design for FPGA-Based Soft-Processors
Eric Matthews et al.
IEEE FCCM, 2019
View PaperVerified adoption, contributor and lineage records, educational use, presentations, articles, and ecosystem data will be added incrementally from named sources.
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