Back to ProjectsStart with GitHub
CVE2 is OpenHW's low-complexity embedded-core family, currently represented by the two-stage CV32E20 processor. The 32-bit, in-order design supports RV32I or RV32E, compressed instructions, and configurable multiplication/division. It suits control-oriented systems where area and energy matter more than peak performance. Students can use it to understand a small modern pipeline, while engineers should pair the RTL with cv32e20-dv and the shared core-v-verif infrastructure for verification work.
Start here
Category: Processor CoresStatus: OpenHW · ActiveBest for: Engineer
At a glance
- Family scope: CVE2 currently contains the CV32E20 core
- Architecture: heavily parameterized 32-bit, two-stage, in-order processor for embedded control
- ISA: RV32I or RV32E, compressed instructions, and configurable multiplication/division; the reviewed configuration has no separate RV32C enable switch
- Origin: forked from lowRISC Ibex and traceable to the PULP Zero-riscy core
- Verification boundary: the local simple testbench is experimental; project verification is maintained in cv32e20-dv and core-v-verif
Further resources
70stars
45forks
SystemVerilogrepository language (GitHub)
Categories
Processor Cores
Tags
OpenHWRISC-VCoreEmbedded-classLow PowerUltra-CompactSystemVerilogRV32MicrocontrollerLow-Area
Suitable For
EngineerStudentContributor
Architecture / Focus
Embedded-classLow-power focus
Contribution ActivityLow Activity
74
Contributors
158
Open Issues
2
Recent Commits (4 weeks)
12
Open PRs
Data as of Sep 28, 2026
Verified adoption, contributor and lineage records, educational use, presentations, articles, and ecosystem data will be added incrementally from named sources.
Related Projects
CV32E40P
CV32E40P is a compact four-stage, in-order 32-bit RISC-V core for embedded and MCU-class systems. It combines RV32IMC with optional floating-point support and PULP custom extensions aimed at code density, DSP-style performance, and energy efficiency. Its clear documentation, mature v1 release, and shared CORE-V verification flow make it useful both for learning a production-oriented embedded core and for integrating or extending a small CPU in an SoC.
CORE-V MCU
CORE-V MCU is a standalone microcontroller-class SoC platform built around CV32E40P and derived from PULPissimo. The repository combines processor integration, memories, peripherals, FPGA targets, simulation flows, and JTAG debug into a complete system rather than providing another CPU core. It is a useful reference for engineers who want to see how a CORE-V core is assembled into an ASIC- or FPGA-oriented MCU, with Nexys A7 and Genesys 2 paths available for hands-on bring-up.