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core-v-cores is the authoritative family map for OpenHW's CORE-V processors. Rather than containing processor RTL, it compares the CVA6, CVW, CVE4, CVE2, and CVA5 families, links to their implementation repositories, and records naming rules, release and RTL-freeze policy, TRL progress, and architectural identity values. Newcomers should use it to understand how the cores relate before choosing a repository; engineers should use its release table to distinguish a family roadmap from the exact maturity of a particular configuration.
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Category: DocumentationStatus: Editorial · ActiveBest for: Student
At a glance
- Artifact type: CORE-V family roadmap and release documentation; each core's RTL lives elsewhere
- Families covered: CVA6, CVW/Wally, CVE4, CVE2, and CVA5
- Configuration distinction: CVA6 includes single-issue CV32A60X and dual-issue CV32A65X RTL configurations; implementation availability and release TRL are separate checks
- Release rule: reaching the target TRL creates a major release, also called an RTL Freeze
- Identification: OpenHW mvendorid 0x602 plus assigned marchid and mimpid values for released cores
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OpenHWRISC-VDocumentationCORE-V FamilyRoadmap
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Data as of Sep 28, 2026
Verified adoption, contributor and lineage records, educational use, presentations, articles, and ecosystem data will be added incrementally from named sources.
Related Projects
CVA6
CVA6 is a configurable six-stage, in-order CORE-V processor family for 32-bit and 64-bit embedded and application-class systems. Its RTL includes both single-issue configurations, such as CV32A60X, and dual-issue configurations, such as CV32A65X. ISA extensions, privilege modes, and virtual memory depend on the selected configuration: application configurations can run Linux, while the embedded CV32A60X and CV32A65X configurations have no MMU or S/U modes. The repository brings together processor RTL, verification, FPGA integration, and documentation for engineers evaluating a core or exploring custom extensions through CV-X-IF.
CVW (Wally)
CVW, also known as CORE-V Wally, is a configurable five-stage SystemVerilog RISC-V processor that spans minimal RV32E designs through feature-rich RV64GC application processors. It combines a broad extension set with optional caches, branch prediction, virtual memory, and standard platform peripherals, and it can boot Linux on FPGA. Its close connection to the RISC-V System-on-Chip Design textbook, examples, and regression flows makes it especially approachable for students while retaining enough configurability for architecture and SoC research.
CV32E40P
CV32E40P is a compact four-stage, in-order 32-bit RISC-V core for embedded and MCU-class systems. It combines RV32IMC with optional floating-point support and PULP custom extensions aimed at code density, DSP-style performance, and energy efficiency. Its clear documentation, mature v1 release, and shared CORE-V verification flow make it useful both for learning a production-oriented embedded core and for integrating or extending a small CPU in an SoC.
CVE2 (CV32E20)
CVE2 is OpenHW's low-complexity embedded-core family, currently represented by the two-stage CV32E20 processor. The 32-bit, in-order design supports RV32I or RV32E, compressed instructions, and configurable multiplication/division. It suits control-oriented systems where area and energy matter more than peak performance. Students can use it to understand a small modern pipeline, while engineers should pair the RTL with cv32e20-dv and the shared core-v-verif infrastructure for verification work.
CVA5
CVA5 is a configurable 32-bit RISC-V soft processor designed specifically for FPGA implementation. Derived from Simon Fraser University's Taiga project, it supports RV32IMAFD and uses parallel, variable-latency execution units so new functional units can be added without forcing every operation into one fixed latency. It is best suited to FPGA architecture research and custom processor prototyping; its completed TRL-3 status means it should be evaluated as a research-ready platform rather than a currently advancing production core.