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OpenHW · ActiveFeatured

CVA6

CVA6 is a configurable six-stage, in-order CORE-V processor family for 32-bit and 64-bit embedded and application-class systems. Its RTL includes both single-issue configurations, such as CV32A60X, and dual-issue configurations, such as CV32A65X. ISA extensions, privilege modes, and virtual memory depend on the selected configuration: application configurations can run Linux, while the embedded CV32A60X and CV32A65X configurations have no MMU or S/U modes. The repository brings together processor RTL, verification, FPGA integration, and documentation for engineers evaluating a core or exploring custom extensions through CV-X-IF.

OpenHWRISC-VCore+7

3,133

1,031

GitHub

Editorial · MatureFeatured

CV32E40P

CV32E40P is a compact four-stage, in-order 32-bit RISC-V core for embedded and MCU-class systems. It combines RV32IMC with optional floating-point support and PULP custom extensions aimed at code density, DSP-style performance, and energy efficiency. Its clear documentation, mature v1 release, and shared CORE-V verification flow make it useful both for learning a production-oriented embedded core and for integrating or extending a small CPU in an SoC.

OpenHWRISC-VCore+7

1,300

551

GitHub

OpenHW · ActiveFeatured

CVW (Wally)

CVW, also known as CORE-V Wally, is a configurable five-stage SystemVerilog RISC-V processor that spans minimal RV32E designs through feature-rich RV64GC application processors. It combines a broad extension set with optional caches, branch prediction, virtual memory, and standard platform peripherals, and it can boot Linux on FPGA. Its close connection to the RISC-V System-on-Chip Design textbook, examples, and regression flows makes it especially approachable for students while retaining enough configurability for architecture and SoC research.

OpenHWRISC-VCore+7

638

576

GitHub

OpenHW · Mature

CV32E40X

CV32E40X is a compact four-stage, in-order 32-bit RISC-V core for compute-oriented embedded systems. Its defining feature is CORE-V-XIF, which lets designers implement custom instructions in an external coprocessor without embedding that logic directly in the CPU pipeline. It is most relevant to engineers and researchers exploring domain-specific acceleration, but adopters should note that the core is considered mature while not currently progressing toward its TRL-5 target.

OpenHWRISC-VCore+6

281

GitHub

OpenHW · Active

CV32E40S

CV32E40S is a compact four-stage, in-order 32-bit RISC-V core designed for security-oriented embedded systems. Building on the CV32E40P lineage, it adds Machine and User privilege modes, enhanced physical memory protection, anti-tampering mechanisms, and the Xsecure extension set. It is a relevant choice when evaluating protection-focused MCU designs; it should not be confused with the lockstep and fault-tolerance work in CVA6-Safe.

OpenHWRISC-VCore+6

163

GitHub

OpenHW · Completed

CVA5

CVA5 is a configurable 32-bit RISC-V soft processor designed specifically for FPGA implementation. Derived from Simon Fraser University's Taiga project, it supports RV32IMAFD and uses parallel, variable-latency execution units so new functional units can be added without forcing every operation into one fixed latency. It is best suited to FPGA architecture research and custom processor prototyping; its completed TRL-3 status means it should be evaluated as a research-ready platform rather than a currently advancing production core.

OpenHWRISC-VCore+6

139

GitHub

OpenHW · Active

CVE2 (CV32E20)

CVE2 is OpenHW's low-complexity embedded-core family, currently represented by the two-stage CV32E20 processor. The 32-bit, in-order design supports RV32I or RV32E, compressed instructions, and configurable multiplication/division. It suits control-oriented systems where area and energy matter more than peak performance. Students can use it to understand a small modern pipeline, while engineers should pair the RTL with cv32e20-dv and the shared core-v-verif infrastructure for verification work.

OpenHWRISC-VCore+7

GitHub

GitHub · Archived

CV32E41P

CV32E41P is an archived four-stage, in-order 32-bit RISC-V prototype derived from CV32E40P. It was created to explore Zfinx and Zce extension work alongside Xpulp custom extensions, and OpenHW records it as a TRL-3 proof of concept rather than a production target. The repository remains valuable for historical implementation study, but new product work should begin with an actively maintained CORE-V core instead.

OpenHWRISC-VCore+6

GitHub

Editorial · ActiveFeatured

CORE-V Verification

core-v-verif is shared functional-verification infrastructure for CORE-V processors. It combines reusable UVM components, simulation Makefiles, verification libraries, utilities, vendor dependencies, and DV plans, with dedicated directories for CV32E40P, CV32E40X, and CV32E40S. Verification engineers can start with the common methodology and then select a core-specific flow. For CVA6, use the verif directory in the CVA6 repository: the current core-v-verif tree does not contain a CVA6-specific directory, although CVA6-related environments can reuse its shared components.

OpenHWRISC-VVerification+7

723

324

GitHub

Editorial · Low activity

FORCE-RISCV

FORCE-RISCV is an instruction-sequence generator for stressing RISC-V processor implementations with large, controllable test programs. It randomizes instructions, registers, addresses, and data while allowing Python templates to constrain generation, control privilege transitions, and shape multi-process or multi-thread scenarios. The generated ELF and assembly outputs can feed RTL simulation, while Handcar provides a Spike-based reference path, making FORCE-RISCV useful to verification engineers who need broader stimulus than hand-written directed tests.

OpenHWRISC-VVerification+5

316

GitHub

Editorial · Low activity

CORE-V MCU UVM

core-v-mcu-uvm is the chip- and subsystem-level UVM environment built to raise the verification maturity of CORE-V MCU toward TRL-5 and beyond. It covers the MCU at chip level and includes reusable environments for blocks such as the APB timer, while consuming the RTL as a submodule. This repository is most relevant to experienced DV engineers because its flows depend on Moore.io packages, simulator-specific tooling, and in some cases licensed Datum verification IP; the stated TRL level is a goal, not an achieved certification.

OpenHWRISC-VVerification+5

GitHub

Editorial · Active

CV-HPDCache Verification

cv-hpdcache-verif is the dedicated verification environment for the CV-HPDCache subsystem, covering the cache controller and prefetcher through Python-driven compile, test, and regression flows. It is useful for engineers working on cache correctness and subsystem integration, but it is not currently a turnkey verification baseline: only CFG1 is documented as working, the SystemVerilog PLRU model is disabled, and the optional AXI5 adapter remains unverified. The cache RTL itself is maintained separately in cv-hpdcache.

OpenHWRISC-VVerification+6

GitHub

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GitHub Repository Snapshot

Public GitHub signals for discovery; they are not a measure of technical quality or project maturity.

Snapshot refreshed Sep 28, 2026

1CVA63,133 stars 2CV32E40P1,300 stars 3CORE-V Verification723 stars 4CVFPU640 stars 5CVW (Wally)638 stars 6CORE-V Cores (Family Landing)373 stars 7FORCE-RISCV316 stars 8CV32E40X281 stars 9OpenHW Programs231 stars 10CORE-V MCU213 stars

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